Setup and function of Radio registers
Aug 18, 2017 04:18
I would like to know what level of detail we can forward to our customers about the setup and
Function of radio registers for the TLSR826x devices (in the register_826x.h file of the current SDK).
Our current customer has detected some comments about different register setup values from technical documentation (following code below).
/****************************************************
RF : begin addr : 0x4e8
*****************************************************/
#define reg_rf_tx_mode1 REG_ADDR8(0x400)
#define reg_rf_tx_mode REG_ADDR16(0x400)
enum{
FLD_RF_TX_DMA_EN = BIT(0),
FLD_RF_TX_CRC_EN = BIT(1),
FLD_RF_TX_BANDWIDTH = BIT_RNG(2,3),
FLD_RF_TX_OUTPUT = BIT(4),
FLD_RF_TX_TST_OUT = BIT(5),
FLD_RF_TX_TST_EN = BIT(6),
FLD_RF_TX_TST_MODE = BIT(7),
FLD_RF_TX_ZB_PN_EN = BIT(8),
FLD_RF_TX_ZB_FEC_EN = BIT(9),
FLD_RF_TX_ZB_INTL_EN = BIT(10), // interleaving
FLD_RF_TX_1M2M_PN_EN = BIT(11),
FLD_RF_TX_1M2M_FEC_EN = BIT(12),
FLD_RF_TX_1M2M_INTL_EN = BIT(13), // interleaving
};
#define reg_rf_tx_buf_sta REG_ADDR32(0x41c)
#define reg_rf_rx_sense_thr REG_ADDR8(0x422)
#define reg_rf_rx_auto REG_ADDR8(0x426)
enum{
FLD_RF_RX_IRR_GAIN = BIT(0),
FLD_RF_RX_IRR_PHASE = BIT(1),
FLD_RF_RX_DAC_I = BIT(2),
FLD_RF_RX_DAC_Q = BIT(3),
FLD_RF_RX_LNA_GAIN = BIT(4),
FLD_RF_RX_MIX2_GAIN = BIT(5),
FLD_RF_RX_PGA_GAIN = BIT(6),
FLD_RF_RX_CAL_EN = BIT(7),
};
#define reg_rf_rx_sync REG_ADDR8(0x427)
enum{
FLD_RF_FREQ_COMP_EN = BIT(0),
FLD_RF_ADC_SYNC = BIT(1),
FLD_RF_ADC_INP_SIGNED = BIT(2),
FLD_RF_SWAP_ADC_IQ = BIT(3),
FLD_RF_NOTCH_FREQ_SEL = BIT(4),
FLD_RF_NOTCH_BAND_SEL = BIT(5),
FLD_RF_NOTCH_EN = BIT(6),
FLD_RF_DN_CONV_FREQ_SEL = BIT(7),
};
#define reg_rf_rx_mode REG_ADDR8(0x428)
enum{
FLD_RF_RX_EN = BIT(0),
FLD_RF_RX_MODE_1M = BIT(1),
FLD_RF_RX_MODE_2M = BIT(2),
FLD_RF_RX_LOW_IF = BIT(3),
FLD_RF_RX_BYPASS_DCOC = BIT(4),
FLD_RF_RX_MAN_FINE_TUNE = BIT(5),
FLD_RF_RX_SINGLE_CAL = BIT(6),
FLD_RF_RX_LOW_PASS_FILTER = BIT(7),
};
#define reg_rf_rx_pilot REG_ADDR8(0x42b)
enum{
FLD_RF_PILOT_LEN = BIT_RNG(0,3),
FLD_RF_ZB_SFD_CHK = BIT(4),
FLD_RF_1M_SFD_CHK = BIT(5),
FLD_RF_2M_SFD_CHK = BIT(6),
FLD_RF_ZB_OR_AUTO = BIT(7),
};
#define reg_rf_rx_chn_dc REG_ADDR32(0x42c)
#define reg_rf_rx_q_chn_cal REG_ADDR8(0x42f)
enum{
FLD_RF_RX_DCQ_HIGH = BIT_RNG(0,6),
FLD_RF_RX_DCQ_CAL_START = BIT(7),
};
#define reg_rf_rx_pel REG_ADDR16(0x434)
#define reg_rf_rx_pel_gain REG_ADDR32(0x434)
#define reg_rf_rx_rssi_offset REG_ADDR8(0x439)
#define reg_rf_rx_hdx REG_ADDR8(0x43b)
enum{
FLD_RX_HEADER_LEN = BIT_RNG(0,3),
FLD_RT_TICK_LO_SEL = BIT(4),
FLD_RT_TICK_HI_SEL = BIT(5),
FLD_RT_TICK_FRAME = BIT(6),
FLD_PKT_LEN_OUTP_EN = BIT(7),
};
#define reg_rf_rx_gctl REG_ADDR8(0x43c)
enum{
FLD_RX_GCTL_CIC_SAT_LO_EN = BIT(0),
FLD_RX_GCTL_CIC_SAT_HI_EN = BIT(1),
FLD_RX_GCTL_AUTO_PWR = BIT(2),
FLD_RX_GCTL_ADC_RST_VAL = BIT(4),
FLD_RX_GCTL_ADC_RST_EN = BIT(5),
FLD_RX_GCTL_PWR_CHG_DET_S = BIT(6),
FLD_RX_GCTL_PWR_CHG_DET_N = BIT(7),
};
#define reg_rf_rx_peak REG_ADDR8(0x43d)
enum{
FLD_RX_PEAK_DET_SRC_EN = BIT_RNG(0,2),
FLD_TX_PEAK_DET_EN = BIT(3),
FLD_PEAK_DET_NUM = BIT_RNG(4,5),
FLD_PEAK_MAX_CNT_PRD = BIT_RNG(6,7),
};
#define reg_rf_rx_status REG_ADDR8(0x443)
enum{
FLD_RF_RX_STATE = BIT_RNG(0,3),
FLD_RF_RX_STA_RSV = BIT_RNG(4,5),
FLD_RF_RX_INTR = BIT(6),
FLD_RF_TX_INTR = BIT(7),
};
#define reg_rf_irq_mask REG_ADDR16(0xf1c)
#define reg_rf_irq_status REG_ADDR16(0xf20)
#define reg_rf_fsm_timeout REG_ADDR32(0xf2c)
#define CLEAR_ALL_RFIRQ_STATUS ( reg_rf_irq_status = 0xffff )
enum{
FLD_RF_IRQ_RX = BIT(0),
FLD_RF_IRQ_TX = BIT(1),
FLD_RF_IRQ_RX_TIMEOUT = BIT(2),
FLD_RF_IRQ_CRC = BIT(4),
FLD_RF_IRQ_CMD_DONE = BIT(5),
FLD_RF_IRQ_FSM_TIMEOUT = BIT(6),
FLD_RF_IRQ_RETRY_HIT = BIT(7),
FLD_RF_IRQ_FIRST_TIMEOUT = BIT(10),
};
enum{
FLD_RF_IRX_RX_TIMEOUT = BIT(2),
FLD_RF_IRX_CMD_DONE = BIT(5),
FLD_RF_IRX_RETRY_HIT = BIT(7),
};
// The value for FLD_RF_RX_STATE
enum{
RF_RX_STA_IDLE = 0,
RF_RX_STA_SET_GAIN = 1,
RF_RX_STA_CIC_SETTLE = 2,
RF_RX_STA_LPF_SETTLE = 3,
RF_RX_STA_PE = 4,
RF_RX_STA_SYN_START = 5,
RF_RX_STA_GLOB_SYN = 6,
RF_RX_STA_GLOB_LOCK = 7,
RF_RX_STA_LOCAL_SYN = 8,
RF_RX_STA_LOCAL_LOCK = 9,
RF_RX_STA_ALIGN = 10,
RF_RX_STA_ADJUST = 11,
RF_RX_STA_DEMOD = 12, // de modulation
RF_RX_STA_FOOTER = 13,
};
#define reg_rx_rnd_mode REG_ADDR8(0x447)
enum{
FLD_RX_RND_SRC = BIT(0),
FLD_RX_RND_MANU_MODE = BIT(1),
FLD_RX_RND_AUTO_RD = BIT(2),
FLD_RX_RND_FREE_MODE = BIT(3),
FLD_RX_RND_CLK_DIV = BIT_RNG(4,7),
};
#define reg_rnd_number REG_ADDR16(0x448)
#define reg_bb_max_tick REG_ADDR16(0x44c)
#define reg_rf_rtt REG_ADDR32(0x454)
enum{
FLD_RTT_CAL = BIT_RNG(0,7),
FLD_RTT_CYC1 = BIT_RNG(8,15),
FLD_RTT_LOCK = BIT_RNG(16,23),
FLD_RT_SD_DLY_40M = BIT_RNG(24,27),
FLD_RT_SD_DLY_BYPASS = BIT(28),
};
#define reg_rf_chn_rssi REG_ADDR8(0x458)
#define reg_rf_rx_gain_agc(i) REG_ADDR32(0x480+((i)<<2))
#define reg_rf_rx_dci REG_ADDR8(0x4cb) // different from the document, why
#define reg_rf_rx_dcq REG_ADDR8(0x4cf) // different from the document, why
#define reg_pll_rx_coarse_tune REG_ADDR16(0x4d0)
#define reg_pll_rx_coarse_div REG_ADDR8(0x4d2)
#define reg_pll_rx_fine_tune REG_ADDR16(0x4d4)
#define reg_pll_rx_fine_div REG_ADDR8(0x4d6)
#define reg_pll_tx_coarse_tune REG_ADDR16(0x4d8)
#define reg_pll_tx_coarse_div REG_ADDR8(0x4da)
#define reg_pll_tx_fine_tune REG_ADDR16(0x4dc)
#define reg_pll_tx_fine_div REG_ADDR8(0x4de)
#define reg_pll_rx_frac REG_ADDR32(0x4e0)
#define reg_pll_tx_frac REG_ADDR32(0x4e4)
#define reg_pll_tx_ctrl REG_ADDR8(0x4e8)
#define reg_pll_ctrl16 REG_ADDR16(0x4e8)
#define reg_pll_ctrl REG_ADDR32(0x4e8)
enum{
FLD_PLL_TX_CYC0 = BIT(0),
FLD_PLL_TX_SOF = BIT(1),
FLD_PLL_TX_CYC1 = BIT(2),
FLD_PLL_TX_PRE_EN = BIT(3),
FLD_PLL_TX_VCO_EN = BIT(4),
FLD_PLL_TX_PWDN_DIV = BIT(5),
FLD_PLL_TX_MOD_EN = BIT(6),
FLD_PLL_TX_MOD_TRAN_EN = BIT(7),
FLD_PLL_RX_CYC0 = BIT(8),
FLD_PLL_RX_SOF = BIT(9),
FLD_PLL_RX_CYC1 = BIT(10),
FLD_PLL_RX_PRES_EN = BIT(11),
FLD_PLL_RX_VCO_EN = BIT(12),
FLD_PLL_RX_PWDN_DIV = BIT(13),
FLD_PLL_RX_PEAK_EN = BIT(14),
FLD_PLL_RX_TP_CYC = BIT(15),
FLD_PLL_SD_RSTB = BIT(16),
FLD_PLL_SD_INTG_EN = BIT(17),
FLD_PLL_CP_TRI = BIT(18),
FLD_PLL_PWDN_INTG1 = BIT(19),
FLD_PLL_PWDN_INTG2 = BIT(20),
FLD_PLL_PWDN_INTG_DIV = BIT(21),
FLD_PLL_PEAK_DET_EN = BIT(22),
FLD_PLL_OPEN_LOOP_EN = BIT(23),
FLD_PLL_RX_TICK_EN = BIT(24),
FLD_PLL_TX_TICK_EN = BIT(25),
FLD_PLL_RX_ALWAYS_ON = BIT(26),
FLD_PLL_TX_ALWAYS_ON = BIT(27),
FLD_PLL_MANUAL_MODE_EN = BIT(28),
FLD_PLL_CAL_DONE_EN = BIT(29),
FLD_PLL_LOCK_EN = BIT(30),
};
#define reg_pll_rx_ctrl REG_ADDR8(0x4e9)
enum{
FLD_PLL_RX2_CYC0 = BIT(0),
FLD_PLL_RX2_SOF = BIT(1),
FLD_PLL_RX2_CYC1 = BIT(2),
FLD_PLL_RX2_PRES_EN = BIT(3),
FLD_PLL_RX2_VCO_EN = BIT(4),
FLD_PLL_RX2_PD_DIV = BIT(5),
FLD_PLL_RX2_PEAK_EN = BIT(6),
FLD_PLL_RX2_TP_CYC = BIT(7),
};
#define reg_pll_ctrl_a REG_ADDR8(0x4eb)
enum{
FLD_PLL_A_RX_TICK_EN = BIT(0),
FLD_PLL_A_TX_TICK_EN = BIT(1),
FLD_PLL_A_RX_ALWAYS_ON = BIT(2),
FLD_PLL_A_TX_ALWAYS_ON = BIT(3),
FLD_PLL_A_MANUAL_MODE_EN = BIT(4),
FLD_PLL_A_CAL_DONE_EN = BIT(5),
FLD_PLL_A_LOCK_EN = BIT(6),
};
// pll polarity
#define reg_pll_pol_ctrl REG_ADDR16(0x4ec)
enum{
FLD_PLL_POL_TX_PRE_EN = BIT(0),
FLD_PLL_POL_TX_VCO_EN = BIT(1),
FLD_PLL_POL_TX_PD_DIV = BIT(2),
FLD_PLL_POL_MOD_EN = BIT(3),
FLD_PLL_POL_MOD_TRAN_EN = BIT(4),
FLD_PLL_POL_RX_PRE_EN = BIT(5),
FLD_PLL_POL_RX_VCO_EN = BIT(6),
FLD_PLL_POL_RX_PD_DIV = BIT(7),
FLD_PLL_POL_SD_RSTB = BIT(8),
FLD_PLL_POL_SD_INTG_EN = BIT(9),
FLD_PLL_POL_CP_TRI = BIT(10),
FLD_PLL_POL_TX_SOF = BIT(11),
FLD_PLL_POL_RX_SOF = BIT(12),
};
#define reg_rf_rx_cap REG_ADDR16(0x4f0) // µçÈÝ
#define reg_rf_tx_cap REG_ADDR16(0x4f0) // µçÈÝ
Could you please sent me more information about it?
Best regards
Leandro Santos
Related topics
| No related topics |
Author's other topics
| Telink 826x BLE Module emulator |
| IDE Manage configuration |
| RTOS Support |
| Telink IDE (FW Debugger) |
Here is the way we think will work out best:
Please come back with some sort of high level description of the tasks you or your customer intend to achieve and we will provide the sample code with proper interface and user instruction. Let's try this approach first and see if it will work out.
Eric